The field of invention relates generally to imprint lithography. More particularly, the present invention is directed to imprint lithographic techniques to form vias suitable for fabricating gate electrodes.
The semiconductor processing industry continues to strive for larger production yields while increasing the operational performance of circuits formed on a substrate. For example, great strides have been undertaken to improve the performance of field-effect transistors. To that end, new gate structures have been developed wherein the gate electrode has a V-shaped cross-section. The V-shaped cross-section of the gate electrode results in a reduced gate length and an enlarged cross-sectional area to prevent an increase in the gate resistance.
U.S. Pat. No. 5,804,474 to Sakaki et al. discloses processes of forming V-shaped gate electrodes employing standard semiconductor fabrication techniques. Important to obtaining the proper shape of the gate electrode is forming a via of complex shape, because the via is used to define the shape of the gate electrode. As a result, Sakaki et al. includes the steps forming a first gate opening in a first resist between a source and a drain formed on a semiconductor substrate. Dummy openings are formed near both sides of the first gate opening. By baking the first resist, convex portions thereof, which rise steeply, are formed between the first gate opening and the dummy openings. A second resist is formed to overlay the first resist convex portions and the first gate opening. The second resist is removed from the first gate opening, and a second gate opening larger than the first gate opening is formed in the second resist above the first gate opening. Metal for the V-shaped gate electrode is deposited through the second gate opening on the sides of the first resist convex portions rising steeply from the bottom of the first gate opening. A lift-off technique is performed to leave the V-shaped gate electrode by dissolving the first resist convex portions and the second resist.
From the foregoing it is seen that standard semiconductor processing techniques are complicated and time consuming thereby increasing the per-unit cost of manufacturing devices including the V-shaped gate electrode. A processing technique that may overcome the drawbacks of the standard semiconductor processes while improving the operation characteristics of the gate electrode structure is known as imprint lithography.
An exemplary imprint lithography process is disclosed in U.S. Pat. No. 6,334,960 to Willson et al. Willson et al. disclose a method of forming a relief image in a structure. The method includes providing a substrate having a planarization layer. The planarization layer is covered with a polymerizable fluid composition. A mold makes mechanical contact with the polymerizable fluid. The mold includes a relief structure, and the polymerizable fluid composition fills the relief structure. The polymerizable fluid composition is then subjected to conditions to solidify and polymerize the same, forming a solidified polymeric material on the planarization layer that contains a relief structure complimentary to that of the mold. The mold is then separated from the solid polymeric material such that a replica of the relief structure in the mold is formed in the solidified polymeric material. The planarization layer and the solidified polymeric material are subjected to an environment to selectively etch the planarization layer relative to the solidified polymeric material such that a relief image is formed in the planarization layer. Advantages with this imprint lithography process are that it affords fabrication of structures with minimum feature dimensions that are far smaller than is provided employing standard semiconductor process techniques.
It is desired, therefore, to provide a process for fabricating vias to facilitate formation of gate electrodes employing imprint lithography.